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Memory Management

The Basics of Memory Management​

Memory management is one of the primary responsibilities of an operating system's kernel. Its tasks include ensuring that processes operate without interfering with each other's memory (except in cases of intentional design, such as inter-process communication), and protecting kernel memory from unauthorized access. This intricate duty is accomplished through various memory models and techniques, including the flat memory model, segmentation, and paging.

Memory Models: Ensuring Isolation and Protection​

Memory models provide the structure for managing memory in an operating system. The flat memory model treats logical memory as identical to physical memory, allowing processes to access memory addresses directly. However, this model lacks isolation and protection mechanisms, rendering it insufficient for modern operating systems. To address this, techniques like segmentation and paging are employed.

  • Segmentation: Segmentation divides memory into segments, each serving a specific purpose. This enhances memory isolation by assigning distinct segments to different processes. However, segmentation can be complex to manage and its protection mechanisms may fall short.

  • Paging: Paging is a more advanced memory management technique. It divides both logical and physical memory into fixed-size blocks called pages and page frames, respectively. This approach facilitates more effective memory protection and isolation. Paging is achieved through the use of a page table, a data structure that maps logical pages to physical page frames.

Paging Theory: Mapping and Protection​

In paging theory, logical memory is divided into pages, and physical memory is divided into page frames of the same size. The page table serves as a critical data structure, providing the mapping between logical pages and physical page frames. The Memory Management Unit (MMU) is responsible for translating logical addresses into physical addresses, ensuring memory protection as all memory accesses are supervised by the kernel.

The MMU not only facilitates address translation but also provides memory protection. Any memory access is mediated by the MMU, ensuring that processes cannot access memory locations that they are not authorized to access. This memory protection mechanism prevents processes from interfering with each other's memory space.

Virtual Memory: Efficient Utilization and Demand Paging​

Virtual memory extends memory management beyond mere protection. While memory protection is crucial, efficient utilization of memory resources is equally important. A key issue arises when a program occupies memory space but remains inactive, a concern particularly relevant for large software applications that are not fully utilized.

Virtual memory addresses this issue through demand paging. Instead of loading an entire program into memory, only the necessary parts, such as starter code, are initially loaded. Additional segments are loaded into memory only when they are needed. This approach conserves memory resources and maximizes CPU utilization.

To manage the loading of pages into memory, virtual memory systems employ page replacement algorithms, such as FIFO (First-In-First-Out) and LRU (Least Recently Used). These algorithms determine which pages to swap in and out of memory based on their usage patterns.

Paging in the x86 Architecture: Enabling and Configuring​

Paging in the x86 architecture is not available by default in real mode and is limited to 32-bit environments, unlike segmentation which can be used in both real and protected modes. Enabling paging involves transitioning to protected mode, achieved by changing the last bit of the control register CR0 from 0 to 1.

The x86 architecture supports different types of paging modes, which can be configured using additional bits:

  • The Physical Address Extension (PAE) bit, located in the fifth bit of control register CR4, enables 4-level paging when set to 1.
  • The Long Mode Enable (LME) bit in a register called IA32_EFER allows switching from protected mode 32-bit to long mode 64-bit. When the PAE bit is set to 1, 4-level paging is enabled.

In 32-bit mode, two page sizes are available: 4KB and 4MB. This mode allows for addressable memory of up to 4GB.

Structure of Linear Memory Address and Page Directory​

A 32-bit linear memory address comprises three components: the Page Group Entry, the Page Table Entry, and the Offset. The Page Group Entry corresponds to a page group address, while the Page Table Entry represents a page address. The Offset specifies the position within a page.

When paging is enabled, logical addresses need to be translated to physical addresses using the page table. The page table resides in memory and provides the necessary mapping between logical pages and physical page frames.

The Page Directory, a crucial component of the paging mechanism, contains up to 1024 entries. Each entry points to a page table, and each page table can hold up to 1024 entries. To locate the page directory, the control register CR3 is used. The base physical memory address of the current page directory is stored in CR3.

Page Directory Entry: Configuration and Protection​

A Page Directory Entry (PDE) is a 4-byte structure that represents the physical memory address of the page table it points to. It also contains flags that control various aspects of memory management:

  • Bit 0: The present bit indicates whether the page table is in memory (1) or not (0).
  • Bit 1: This bit specifies the read/write permissions for the page table (0 for read-only, 1 for writable).
  • Bit 2: Determines the privilege levels that can access the page table (0 for privilege levels 0, 1, and 2, 1 for privilege level 3).
  • Bit 3: Controls the writing policy of the page table (0 for write-back, 1 for write-through).
  • Bit 4: Specifies the caching policy (0 for caching, 1 for no caching).
  • Bit 5: The access bit is set by the processor when the page table is accessed.
  • Bit 7: Determines the page size (0 for 4KB, 1 for 4MB).

These flags and configurations enable the kernel to manage memory protection, caching, and other critical aspects of memory management effectively.

Page Table: Mapping Logical to Physical Memory​

In the case of a 4KB page environment, each page table is referred to by an entry in the page directory. Each page table can hold 1024 entries, and these entries map logical pages to physical page frames. To locate a page's base physical memory address, the corresponding page table entry is used. The offset within the page is then added to this address to obtain the final physical memory address.

The entry structure of a page table is similar to that of a page directory entry. However, there are some differences, such as the inclusion of a dirty bit. This bit, marked as "dirty," indicates that a page has been modified and needs to be written back to memory. The dirty bit is crucial for efficient memory management and cache management.